Research On Low-Power Network-on-Chip Design And Mapping

As VLSI (very large scale integrated circuit design Very Large-Scaled Integrated Circuit) technology and the technological level of the continuous development of single-chip integration of multiple processing units has become possible, you can run the application of homogeneous or heterogeneous. However, the IC’s power consumption has become a big bottleneck, limiting further improve its performance as well as the number of cores on a single chip the increase. In fact, the problem is not to limit energy consumption chip performance further improved, but also led to a higher hot region of the chip, reducing the life of the chip, the chip and chip supply network design for testability, etc. have brought a great challenge. In addition, the energy consumption for battery-powered mobile equipment is a more critical issue. NoC (Network-On-Chip) as the preferred architecture for massively parallel processor, chip design is the future direction of development, it has not only been widely used in high-performance servers and other large-scale computing systems, also mobile and wireless communication terminals and other embedded high-performance SoC (System-On-Chip) design used. So in recent years, on the one hand, to promote energy conservation awareness of network design low power chip technology, on the other hand, as a result of energy consumption increased chip temperature rises, and thus the performance of the chip and also promote the stability of the industry and academia for low-power chip network research.Paper have a detailed analysis of the on-chip network power sources, including:to analyze from a circuit-level dynamic power and static power consumption, the level of analysis from the power modeling node power, link power conversion power consumption. Papers on-chip network power sources based on the analysis presented NoC power consumption affect the main factors. Papers from the physical hardware layer, system software layer, application layer algorithms were low-power on-chip network technologies are analyzed and summarized, and elaborate on-chip network mapping problem based on the low-power chip network mapping model. Subsequently, the paper proposes an improved ant colony-chip network mapping algorithm, and to verify that the mapping algorithm for low-power chip network performance improvements, combined with the specific application of simulation experiments. This paper compares the improved ant colony algorithm and general ant colony algorithm, particle swarm optimization mapping result of pros and cons.5groups selected simulation experimental results were analyzed performance. Experimental results show that the improved ant colony algorithm can convergence speed, stagnation and other aspects to achieve better performance; experimental data also show improved ant colony algorithm for comparing general ant colony algorithm, the optimal ratio of the average power consumption of69%. Improved ant colony algorithm comparison, the average particle swarm optimization power ratio of59%. Experimental results show that the improved ant colony algorithm to obtain a mapping solution can be achieved in a power function of lower power consumption.