Research On Network-on-chip Mapping For Power Consumption And Delay Optimization

With the rapid development of semiconductor technology and the continuous improvement of technology level,more and more IP cores can be integrated on a single chip,and the SoC(System on Chip)processor structure is gradually developing toward multi-core and heterogeneity.The problem caused by the SoC based on bus structure is more and more obvious.In order to better meet the application needs and improve system performance,NoC(Network on Chip)came into being.NoC is a new SoC communication architecture.It borrows the idea of computer network and mainly uses technologies such as data routing and packet switching.From the point of view of architecture,NoC solves the SoC bus structure's problem of poor scalability caused by limited address space,low communication efficiency caused by time-sharing communication,and increase in power consumption and area caused by global clock synchronization.Although NoC solves a series of problems in the bus structure,with the increasing number of cores and the increasing complexity of applications,the power consumption and delay of NoC also increase,which is a factor that must be considered because it affects the improvement of overall performance.Meanwhile,it also reduces the life of the chip and affects the stability of the chip operation.NoC's power consumption and delay are affected by many factors.The design of NoC topology,selection of routing algorithm and mapping algorithm are important aspects that need to be considered in designing low-power,low-delay NoC.Because the communication distance between the nodes on the chip will greatly affect the power consumption and delay of the system.Therefore,in addition to adopting efficient topology and routing algorithm,it is more necessary to design an effective NoC mapping algorithm to reduce the average distance between nodes with large traffic,thereby reducing the power consumption and delay of the system.Aiming at the problems of NoC mapping optimization and traditional mapping algorithm.This paper mainly does the following research.Firstly,the mapping is divided into two phases.In the first phase,the task nodes are assigned to the appropriate IP cores.In the second phase,the IP cores that have been bound to the task are mapped to the NoC platform to settle their specific locations in NoC.Then this paper analyzes the different characteristics of the two phases mapping,and uses different schemes for mapping optimization.Secondly,with power consumption and delay as optimization targets,this paper establishes NoC power consumption model,delay model and multi-objective optimization model to analyze and evaluate the advantages and disadvantages of the NoC mapping scheme.Thirdly,the paper proposes a mapping scheme based on KL_SA(Kernighan-Lin with Simulated-Annealing)algorithm.This scheme combines the advantages of KL algorithm efficient partitioning and SA algorithm for searching global optimal solution,which can effectively reduce the communication distance between nodes with large traffic and quickly get the solution closest to the optimal solution,thus reducing the system's power consumption and delay.And the mapping scheme proposed in this paper adds memory function,which can memorize the current best state to avoid losing the current optimal solution in the process of jumping out of the local optimal solution.Thus,the global approximate optimal solution is obtained,and the mapping result is further optimized.Finally,in order to verify the effectiveness of the scheme accurately,three applications are simulated by BookSim simulator.The experimental results show that under the single-objective optimization condition,the power consumption is reduced by 15.0% and 14.1% on average,and the delay is reduced by an average of 11.5% and 13.4% compared with the simulated annealing algorithm and the genetic algorithm.Under the multi-objective optimization condition,although the optimization degree of a single target is slightly reduced,it has a better effect on the overall optimization of power consumption and delay,and the power consumption and delay optimization effects can be adjusted by setting different weight ratios to better meet the needs of different applications.Therefore,the mapping scheme proposed in this paper has a good optimization effect on the NoC.