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The Research On Low-Energy And Low-Latency Of Network-on-Chip

Posted on:2010-05-31Degree:MasterType:Thesis
Country:ChinaCandidate:H Y TaoFull Text:PDF
GTID:2178360275982522Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Network-on-chip(NoC) is an important direction of development of system on chip, and the power consumption as well as speed are the main constraints in the design of NoC. With the increase in bandwidth requirement in the NoC, the energy consumption of communication infrastructure accounts for a large proportion of the system, which is still gradually increasing; At the same time, because of the increase in terms of speed and the number of processor cores, the communication delay between these processor cores greatly affects the overall performance of the system. With the requirement for high performance embedded computing increasing, as well as the issues of heat elimination and limited battery life prominent, energy consumption and delay have became the important issues that must be addressed for NoC to practical application.This paper focuses on the energy consumption and delay of the NoC. Through the analysis of the advantages and disadvantages of the current research on low energy consumption and low delay design technology, the thesis presents an algorithm used for solving parallel communication arc with labeling in terms of the balance of concurrent traffic on communication links in the communication of the architecture level. With the relative predictability of the communication between the IP cores and the timing relationship of these communications, this algorithm solves the concurrent traffic of each communication link. Further, the balance of the concurrent traffic of the link can be used to reduce the delay. Base on the proposed algorithm and combination of low energy consumption mapping with ant colony optimization algorithm in the NoC, this thesis designs an integrated scheme for low energy consumption and low delay. Through the product of the standard deviation of the link's concurrent traffic and energy consumption as a target evaluation function, we achieve an integrated optimization of the energy consumption and delay in the process of ant colony optimization.To comprehensively evaluate the optimization effect of the energy consumption and delay of the NoC system, this paper uses energy-delay product(EDP) as the metrics of energy-performance efficiency. Based on this metrics, we conduct some simulation experiments for the proposed integrated optimization scheme through using the SystemC-based NoC simulator. The results show that the presented method used in this paper is better than the method of link balance in terms of energy-performance efficiency.
Keywords/Search Tags:Network-on-Chip, Energy/Power Consumption, Delay, IP Mapping, Ant Colony Optimization, Concurrency Communication
PDF Full Text Request
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