Design And Implementation Of Reconfigurable Computing Hardware Platform Based On FPGA

With the continuous development of information technology and computingscience, FPGA-based reconfigurable computing technology, which is characteriszedby flexibility, versatility, high efficiency, etc, has been becoming the main focus ofhigh-performance computing research. According to the requirement ofreconfigurable computing applied to high-performance computing, the design ofreconfigurable computing hardware platform, the research foundation ofreconfigurable computing, will face more challenges, such as large amounts of datacache, high-bandwidth data exchange interface, controle of reconfiguration process,driver of peripheral and packaging of computing resources.To solve these problems, based on the reconfigurable hardware platform forlarge-scale and parallelization computing on the demand of the principles ofreconfigurable computing, a design of reconfigurable hardware platform is proposedby using Virtex-6FPGA, which includes PCIe interface, Ethernet, DDR3SDRAMand the SOPC supporting reconfiguration. On the aspect of hardware, signal integrityis improved through the design of high-speed hardware constraints. For the limit ofcommunication bandwidth of input and ouput, a high-bandwidth PCIe interface wasimplemented, which use the Endpoint IP hardware core in FPGA. Then, an Ethernetinterface which satisfies the demand of network data communication is designed bythe combined utilization of an Ethernet PHY layer chip and an Ethernet MAC layerIP core. Large capacity and high bandwidth data storage solution, consisted of off-chip DDR3SDRAM controlled by MPMC IP, is proposed, which overcome theexecution efficiency caused by amouns of data buffer, in the meanwhile somesignificant technology methods like allocation of FPGA resources and design constraints of PCB, etc are used. On the aspects of the firmware, to overcome thedifficulities in reconfigurable computing, such as pheripheral and package ofalgorithm IP, the framework of the user common IP core was proposed, morespecifically, including the design of the SOPC supporting reconfiguration, as well asIP core of data exchange interface and data storage.Above all, this paper has focused on the design and implementation of areconfigurable computing hardware platform. Experiment results show that thebandwidth of the PCIe data interface is701.67MB/s, and the Ethernet interface cancommunicate with the network in48.7Mb/s. It has also implemented the datastorage system that is1GB capacity of DDR3SDRAM. The throughput of thecommon user IP core framework can be achieved742.6MB/s. The SOPC systemsupport for reconfigurable technology meets the high parallel reconfigurablecomputing needs.