Research On System Level ESD Protection Of Integrated Circuits

With the birth of the first semiconductor Integrated Circuit (IC) in1958, IC industry development has brought rapid changes to people’s lives and work. With the rapid development of electronic information technology, semiconductor devices especially like the consumer electronics and portable products which have stringent requirements of the motherboard area, growing tendency of miniaturization, high density and multi-functional, are susceptible to electrostatic discharge (ESD) damage. Transient voltage suppressors (TVS) mainly used for system-level ESD protection are studied in this dissetation. Besides the TVS based on Zener diode, the feasibility of TVS devices based on CMOS process is also researched. Some novel TVS devices based on0.6μm SOI process,0.5μm BCD process,0.35μm CMOS process,0.18μm CMOS process and65nm CMOS process are proposed and tapeout for further verification. The main research mainly deals with the following aspects:1, Combined with the advantages of the traditional transient voltage suppressors (TVS), the implementation of the multi-channel TVS structure based on the zener diode has been studied. To improve the robustness of the TVS devices, a novel TVS structure with porus channel to solve the the ESD current uniform issues is proposed.2, A novel Zener diode triggered silicon controlled rectifier (ZTSCR) structure is proposed based on0.35μm CMOS process. The effects on the different position of zener diode are also studied. Results show that the trigger voltage of the proposed structure is reduced dffectively compared with the traditional silicon controlled rectifier (SCR) structure and the ZTSCR structure with the zener diode between the N-well and P-well has a minimum second trigger voltage.3, Floating N-well technology is proposed to improve the holding voltage of low voltage triggered silicon controlled rectifier (LVTSCR) based on65nm process. The floating N-well area blocks the current from anode to cathode of the LVTSCR structure and widens the base width of the parasitic NPN transistor longitudinally without increasing chip layout area. The holding voltage of the LVTSCR structure is improved effectively by inserting the floating N-well area.4, Further optimization of ESD key parameters like the trigger voltage and holding voltage are achieved by using diode to trigger the LVTSCR (DLVTSCR) structure based on0.35μm CMOS process. A whole TVS structure is designed using DLVTSCR as TVS core device.5, Lateral Insulated Gate Bipolar Transistor (LIGBT) structure is studied for high voltage ESD protection based on0.6μm SOI process. Higher holding voltage is obtained by increasing the emitter and collector region resistance of the parasitic BJT strcture.6, The degradation phenomenon of LDMOS embedded SCR (SCR-LDMOS) is investigated by applying multiple TLP pulses. Supported by the similar degradation behavior of drain avalanche breakdown, the phenomenon is explained with base push-out effect. Research on the degradation phenomenon provides a reference for the design of high voltage ESD protection.