The System Modeling And Circuit Design Of A Delta-sigma Fractional-N Frequency Synthesizer

IEEE802.11is universal standard of wireless LAN. In the RF transceiver which support802.11b/g/n wireless communication standard, frequency synthesizer provides a systemdesired carrier. The phase noise and the tuning range of the output signal directly determinethe signal quality and maximum transceiver frequency range of the entire RF transceiversystem. Therefore, it’s very important for the entire RF transceiver system to design a lowphase noise and high resolution frequency synthesizer.In this paper, we use the top-down design method, combine with the system levelanalysis of frequency synthesizer, to design a Delta-Sigma fractional phase locked loop whichoutput frequency is from4.5GHz to4.9GHz.This paper analysis, model and optimization the PLL output phase noise. Analysis eachmodule circuits’(PFD, charge pump, loop filter, VCO and divider) equivalent output noise,and design a method of reducingΔΣ modulator quantization noise. Based on these modules,we use the Verilog-A hardware description language to design the frequency synthesizerbehvaioral module. Using behavioral models’ bottom-up verification, we put the noisecharacteristics in the behavioral models, making the frequency synthesizer behavioral modelroughly close to the actual traditional the circuit transistor level simulation results.Through the study of the system-level model, estimated frequency synthesizer’s phasenoise, loop parameters and fractional spurs indicators. On the basis of these indicators, designthe circuits. The analog circuits include a high speed, low power consumption and withoutdead zone PFD, a simple structure and stability charge pump, a switched capacitor arrayvoltage-controlled oscillator. The digital circuits include a fast adaptive calibration system,and aΔΣ modulator.Finally, this paper uses TSMC0.18μm CMOS process to design the monolithicallyintegrated fractional-N PLL. The test results show that the PLL output frequency is form4.5GHz to5.0GHz; the frequency resolution is38.15Hz; lock time is less than20μs; the phasenoise is-100dBc/Hz@100KHz,-120dBc/Hz@1MHz. Meet the design specifications of thephase-locked loop. The top-down design process used in this paper, provide some reference for improvingthe design efficiency of analog integrated circuits.