Study And Design Of16Mbit FPGA Configuration Memory

Accompany with the develop of the semiconductor technology and digitalintegrated circuit, FPGA (Field Programmable Gate Array) because of its own on-chipnumerous programmable resources and rapid flexible field Programmable characteristic,has been widely used in many fields. SRAM-based FPGA must use one or more piecesof non-volatile memory with its application together to store the FPGA configurationdata, because of SRAM-based FPGA will lose its function when after power down. Asincreasing the size of the FPGA, the capacity of the configuration memory is requiredmore and more, and also needs the configuration memory to have a very fast accesstime. Furthermore, in order to match the power-up, power-down and reset timing of theFPGA and the characteristics of in-system debuggable and programmable, the universalmemory generally not act as the best ideal choice of FPGA configuration memory.Therefor, the specifically customized configuration memory for the FPGA will have abroad market and development prospects as the same as the FPGA.The study purpose of this topic is achieved a FPGA configuration memory whichhave sixteen million capacity and can be adapted to the configuration mode of majorFPGA. The experiencing Approach are in-depth analysis of foreign advanced FPGAconfiguration memory design technology and combined with the actual level of existingtechnology and the experience of previous relevant projects, then attempted to form thedesign method of the FPGA configuration memory and completed the design of the“16Mbit FPGA configuration memory”.Due to limited by the technology barriers of the Flash Memory patents, wanting tocustomize the Flash Memory array module for the “16Mbit FPGA configurationmemory” will need to spend very expensive costs and a long time. So the technicalapproach of this topic is choosing the suitable universal Flash Memory IP which isprovided by the foundry that has the authorized of Flash Memory patent technology,then around the Flash Memory IP to design the on-chip decompression circuit,multi-version configuration file selected circuit and in-system programming circuit. Thedesign of the “16Mbit FPGA configuration memory” utilized forwarde digital circuit design process and implemented design-code written, functional simulation, prototypeverification, synthesis, placement and routing, and post-simulation design steps, thencompleted tapeout.The team has completed the functional verification of the “16Mbit FPGAconfiguration memory” through joint test with the FPGA and its programmed software.The test results match the design requirements. The “16Mbit FPGA configurationmemory” can adapt to a variety of major FPGA configuration application mode, toachieve the desired objectives. The design techniques can be used for the design andproduct development of similar projects in the future.