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Based On Fpga-evolutionary Systems Design And Research

Posted on:2011-07-08Degree:MasterType:Thesis
Country:ChinaCandidate:H X BoFull Text:PDF
GTID:2208360305497734Subject:Microelectronics and Solid State Electronics
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Evovable hardware is the hardware that can dynamically and independently change its structure and behaviour when interacts with the enviorement.The basic character of EHW is self-orgnization,self-adaption,self-restore, there are wide prospect of EHW in intelligent communication network, intelligent sensor,pattern recognition and artificial intelligence.For the FPGA can change its function conveniently through different configuration bit stream,early in 1992 international experts in artificial intelligence Dr. Hugo de Garis proposed the concept of EHW based on FPGA. Currently,EHW based on FPGA has become the most popular way in the evolvable hardware research.In this paper, the concept of EHW is introduced,and the recent research of EHW based on FPGA is analysed.From analysis of the basic part of EHW:reconfigurable circuit model,genetic algorithm, and configuration of reconfigurable circuit,the solution to improve EHW based on FPGA is proposed and complete evolution system based FPGA is designed and verified.First, the mainstream implementation of EHW based on FPGA:virtual reconfigurable circuit model (VRC) is intrduced and analysed in this paper.one VRC model based on 3-input LUT with direct connection is proposed from the view of function cell and interconnection, and this model is verified through the evolution ecperiment on Altera DE2 platform.Second, analyse the basic parts of EHW:genetic algorithm and circuit configuration,and participate in design and verification of the CPU+FPGA reconfigurable system chip FDP2009-2-SOPC.This chip improve the implementation of evolution system from 3 aspects:one is the special configuration port of FPGA which can implement fast partial configuration to FPGA through CPU,can realize on-chip evolution.the second one is:configuration of FPGA in one word can be implemented when few bitstream is changed in every interation of evolution,for row-column decoder in bitsream strcture of FPGA,it can improve the time of partial configuration.the last one is the genetic algorithm accelerator designed for characrteristic of genetic algorithm,the accelerator can improve the implementation time of genetic algorithm.At last,one complete on-chip evolution system is built based on the reconfigurable system chip above, and the experiments to verify the improvement of evolution system caused by genetic accerlerator and partial reconfiguration are did.
Keywords/Search Tags:EHW, VRC, on-chip evolution system, FPGA, genetic algorithm accerlerator, partial configuration
PDF Full Text Request
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