Functional Verification Of EECTRL IP Based On VMM

With the development of the integrated circuit technology, the increase of thefunctional complexity of chip and the chip market demand time-to-market，which makethe validation work face increasing pressure and challenges.The low success rate of thefirst tape out and the long research and development cycle of chip is a commonphenomenon in the industry.And the reason of failing single tape out is functionaldefects caused by incomplete functional verification.How to enhance the success rate ofsingle tape out and shorten the development cycle of chip by improving the verificationmethod is the focus in this paper.The main content of this thesis is building the verification platform of EECTRLusing VMM verification methodology based on SystemVerilog.The verificationplatform has many advantages which can improve verification efficiency and shortenresearch and development cycle of product,for example,constrainted randomstimulus,assertion technology,object-oriented,resuable etc.The verification method isbased on coverage-driven,by analyzing the code coverage and functional coverage toensure the completeness of functional verification of chip and improve the success rateof first tape out.The procedure of building the whole verification platform has beenresearched in detail,the function and implementation ways of verification componentshave been illustrated, how to complete desired function verification using constrainedrandom test and assertion have been explained,the data flow of verification environmentand how to check the result of functional simulation automatically have beenanalyzed.The debugging process and method of verification platform have beenexpounded.At last,the result of coverage statistics of EECTRL module reached theexpected verification requirements,the functional simulation verification completed.