Design Of Reed-Solomon Decoder For QAM Demodulate IC

Reed-Solomon error correction is a very important technology which exists in today's digital communication systems. Because of its excellent error correcting ability, Reed-Solomon codes has extensive applications in storage devices, communication and broadcasting, in particular forming part of the specification for the ETSI digital cable television standard, known as DVB-C.Hardware implementations of coders and decoders for Reed-Solomon error correction are complicated and require some knowledge of the theory of Galois fields on which they are based. This paper describes the underlying mathematics and the algorithms used for coding and decoding, with particular emphasis on their realization in logic circuits. Based on the analysis and comparison of several representative decoding algorithms, we derived a VLSI solution for our design goal which plays an important role in the FEC block of a new HDTV demodulate chip.On the other hand, we presented all the modules of this RS(204, 188) decoder which is fully compatible with the DVB-C standard, with particular emphasis on the key-equation solver (KES) block. Through the whole process of VHDL coding, RTL simulation and synthesis, the proposed RS decoder has been implemented with the Chartered 0.35μm CMOS standard cell technology. In the end of the paper, relative simulation and test results together with the parameter of the decoder are provided.