Research And Design Of Analog Baseband And Analog - To - Digital Converter For Short Distance Wireless Receiver Receiver

Due to its low power, narrow band and usage in the unlicensed ISM (Industry, Science and Medical, ISM) band, short range devices (SRDs) are widely used in the applications such as remote auto-control of households, buildings and automobiles, wireless sensor networks, alarms, medical device implantation, etc.. Although SRDs has a limited data rate, which generally ranges from tens of kb/s to several hundreds of kb/s, they greatly improve the automation and intellectualization of human’s daily life. Therefore, they will be getting more and more market interest in the following decades of years.The designed receiver in this thesis follows the standards of EN300220. Firstly, from the aspect of system design, in order to meet the stringent requirement of low power and the standard, the low-IF receiver is selected and the image problem is largely relieved by utilizing the quadrature mixer combined with the complex filter. Besides, the analog double quadrature sampling is adopted to sample the complex intermediate frequency signal. The IF signal is down converted to the baseband at the same time, so that a low pass∑-△modulator can be used to implement the analog-to-digital conversion of the sampled signal. With this scheme, the power consumption of the system is further reduced.Secondly, the circuit design of the analog baseband (ABB) and the analog-to-digital converter (ADC) is described in this thesis. The ABB circuit consists of a preceding VGA1with moderate gain range, a complex filter and a following VGA2with large gain range. And the ADC consists of an analog quadrature sampling circuit realized by simple switch operations and a single-loop2nd-order2bit I-A modulator with dynamic element matching to achieve high precision analog-to-digital conversion.The receiver is implemented in SMIC0,13μm RF CMOS process. The measurement results show that the complex filter has an IRR of46dB. The VGA2has a gain range of about-23-37dB and IIP3of-30-20dBm. The ENoB of the ADC within the bandwidth of9.6kHz is about12bit. The overall circuit dissipates3.6mW with1.2V power supply. And according the post-layout simulation results, the NF and MP3of the receiver is7dB and-21dBm, respectively and consumes9.6mW with1.2V power supply. The receiver is still under test. Finally, the total chip area of the fully integrated transceiver is about3.1mm×2.4mm.