Research On The Key Technology In DC-OFDM Receiver And Implementation Of UWB Baseband Chip

Orthogonal frequency division multiplexing (OFDM) is a promising technique for achieving high bit rates and high reliabilities required for wireless communication. This new technique has gained increased interest for its high bandwidth efficiency and robust performance in multipath dispersive environment. DC-OFDM based UWB technique has been selected as the standard of information technology-Telecommunications and information exchange between systems of China, which provides a Dual-Carrier (DC) structure in RF part, so that the baseband signals will be modulated onto two different carriers. This structure reduces the requirements for some critical hardware implementations of RF and baseband circuits, achieves frequency diversity and improves the flexibility of use of the frequency spectrum.In the digital baseband receiver, synchronizer is a crucial module. Its performance directly affects the performance of the communication system. Synchronization technology is usually divided into symbol and frequency synchronization. Symbol synchronization is used to obtain the starting and ending position for the Fast Fourier Transform (FFT) window. Frequency synchronization is used to solve the signal amplitude attenuation and interference among subcarriers due to carrier frequency offset (CFO).The proposed synchronizer is mainly divided into three parts. The first part is timing synchronization including frame detection and symbol synchronization. In order to get lager adjustable range and fast convergence, a double close-loop AGC is proposed. After the adjustment of two closed-loops, variable gain amplifier in RF is set to a suitable gain in accordance to the estimated power. The third part is estimation and compensation of CFO and IQ mismatch. Carrier frequency offset (CFO) is caused by the carrier frequency deviation of RF transmitter and RF receiver, which introduces the ICI (Inter Carrier Interference,) within the OFDM symbols, IQ mismatch is caused by the difference between I path and Q path (such as the filters are not exactly the same), which introduces the image frequency interference of the ideal signal. These non-ideal factors will worsen the system performance, therefore they need to be estimated and compensated.In consideration of large amounts of operation circuits in the synchronizer, this paper introduces the CORDIC algorithm with pipeline structure. The algorithm realizes the cotangent function, square root function and logarithm function, which greatly improved the computational speed. The synchronizer is synthesized using 0.13um COMS process and the frequency is 132MHz. The results is analyzed and contrasted.Finally, this paper gives the implementation of the chip. Both the chip and the system is tested and verified, the results is shown in the paper.