Based On The Vmm Soc Chip Research And Implementation Of Hardware And Software Collaborative Verification Platform

Chip design and verification are most important aspects of chip front-end development. Due to the scale of SoC increases daily and IP core multiplexing comes out, the front-end verification is more difficult and time-consuming step in SoC developing. Usually, Chip design and verification are carrying out in parallel:dividing the test points, setting up verification environment, selecting verification method and writing case for testing are required in the verification step. After finishing RTL codes of chip design, the verification of the design must be converged correspondingly in order to completely verify functions of chip. Currently, it is difficult to establish a platform, which is suited for chip’s software and hardware collaboration and ensures the reusability and high efficiency of verification environment.This article is based on the demand of front-end development of one kind of SoC VOIP voice chip. After deep analyzing the tunction requirements of this chip and achieving design, the detailed verification scheme is given, the specific verification test point is divided. And considering the characteristics of this kind of chip, the verification environment for software and hardware collaboration is set up, the verification algorithm is shown and the complete verification of this chip is realized.The contents of this task are:1. Exploit VMM method to establish verification environment. The way for establishing reusable unit verification environment is presented. Self-testing ability is also included in this reusable unit.2. Complete construction of environments from unit verification to system hardware verification. The method of setting up system hardware verification environment is shown, and the interrupt is introduced into the environment.3. Finish building software verification environment. The mechanism for scheduling and management of two kinds of software are built up, and the software is implanted into the verification environment.4. Using various scripts and collaborating between software and hardware verification environment on chip’s verification. And the verification algorithm related to the characteristics of chip is depicted.5. After generating netlist file from RTL codes and achieving design for testability, place&route, in order to guarantee the quality of the chip, post-simulation is included as well.This article achieves the construction of simulation environment of SoC chip making software and hardware work collaboratively, which runs faster, has high verification efficiency, saves the time-cost of chip front-end development, realizes the complete verification of chip functions, and guarantees the quality of the chip. In the article, the verification methods for key modular are efficient and applicable which could be employed as universal methods of the front-end development of ASIC program.