Layout verification for mixed-domain integrated MEMS

As design of integrated MicroElectroMechanical Systems (MEMS) mature, there is an increasing need for verification tools for such layouts. This requires a mixed-domain layout-versus-schematic (LVS) tool capable of extracting an integrated schematic from the mixed-domain layout and verifying it against the design schematic. This thesis presents an extraction methodology for integrated MEMS designs capable of capturing domain-specific parasitics. A custom schematic-versus-schematic (SVS) tool is also presented. The custom MEMS SVS tool compares the parameters and connectivity of schematic elements between the extracted and design schematic. It also highlights the symmetry information in the layout.; Efficient data structures and algorithms used for representation and recognition of complex multiconductor MEMS layouts are discussed in this thesis. To account for the diversity of fabrication processes in MEMS, the extraction methodology uses technology independent symbolic layer processing. This allows easy adaptability of the extraction flow to any new process. This capability is demonstrated using two different fabrication processes for suspended MEMS. Unlike previous tag-based verification tools, the extraction methodology introduced in this constructs the schematic representation directly from the layout without using any user hints. It also exploits hierarchy in structured MEMS designs in its representation and recognition algorithms. The parameters used for recognition and the library of elements can be easily modified by the user by modifying the library files. The automatically extracted schematic is then simulated using fast schematic level simulators capable of handling mixed-domain integrated schematic to verify the behavior of the system. The verification flow can be easily implemented for other MEMS domains. Two representative domains, suspended mechanical MEMS and microfluidic systems, are chosen as focus domains in this thesis. The design flow used for implementing the prototype extractor for these two domains can be used to implement extractors for other MEMS domains. The impact of the verification flow using extraction and LVS is demonstrated using a wide variety of examples. Such a verification methodology is essential for fast iterative design cycles needed for complex MEMS designs.