VLSI Design Of Rate-Distortion Optimized Truncation Based On JPEG2000

The ne xt generation static image compressing standard JPEG2000employs theDiscrete Wavelet Transform (DWT) and the Embedded Block Coding with OptimizedTruncation (EBCOT), receiving a better coding efficiency and reconstruction qualitytha n other traditional algorithms.We mainly research into the design and high effective VLSI implementation of theRate-Distortion Optimized Truncation algorithm of the T2part in JPEG2000. Accordingto the requirements of image resolution, compression rate, number of truncation layers,having ROI or not and the reliability of JPEG2000, we propose a fast singular pointelimination method suitable to hardware implementation, which is able to achieve thebest performance. We design and implemented the entire Rate-Distortion OptimizedTruncation VLSI architecture. In the system, the key logic and state control circuit areprotected via Triple Modular Redundancy (TMR) and EDAC method and thereforehave certain ability to resist the Single Event Upset (SEU); a random error in one framewill be recovered in the next frame by using a frame independe nt design. We verifiedthe architecture on FPGA and it turned out that this module is able to meet therequirement in quality, complexity and reliability.