Research On The Key Technologies Of JPEG2000 Still Image Compression And VLSI Implementation

Image compression techniques are very important for the storage and transmission of the huge data in the modern image processing. Nowadays, the traditional still image compression techniques, e.g., the well-known JPEG standard, could not meet the rapidly increased demand for the high quality low bit-rate images in various emerging applications. The latest still image compression standard JPEG2000 adopts Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT), which achieves much better coding efficiency and image quality than the traditional methods. With its excellent performance and prominent features, JPEG2000 will no doubt become the main-stream in the image compression field in the future; therefore, high attention is paid to its VLSI realization. This dissertation deeply accessed the hardware implementation techniques for DWT and EBCOT in JPEG2000, accomplished the design and manufacture of the DWT chip THSCLA and JPEG2000 encoder THJ2K respectively.THSLCA is the first VLSI implementation of the Spatial Combinative Lifting Algorithm (SCLA) in the world. SCLA effectively reduces the number of multiplications with a ratio of 42% (regarding 9/7 wavelet filter) and 50% (regarding 5/3 wavelet filter) respectively, compared with the JPEG2000 recommending lifting base implementation. THSCLA performs 5-level Mallat wavelet decomposition for 9/7 lossy filter with a relatively small penalty of only 16 adders and 5 multipliers. It was designed and fabricated by using Korean DONGBU 0.25um 1P4M CMOS technology with the scale of 25K equivalent gates plus 101KBits SRAMs and the area of 4.9mmx4.8mm. The test showed 110MHz of the maximum working frequency and 1.4mW/MHz of the power consumption. THSCLA can process 25 frames per second for the image with resolution of 1280x1024x24bits (YUV422 full color) at 50MHz, which is in the advanced level among the known published DWT chips. THJ2K is the first JPEG2000 encoder integrated with the DWT IP-core of SCLA in the world. It decreased the edge-noise by using 512x512 large image tile structure; reduced the memory requirement for the wavelet coefficients by the technique of dynamic memory control; and implemented the accurate on-chip bit-rate control by truncating bit-stream in parallel according to the prediction of the rate-distortion threshold. It was designed and fabricated by using Shanghai SMIC 0.18um 1P6M CMOS technology with the scale of 350K equivalent gates plus 1Mbits SRAMs and the area of 4.9mmx9.9mm. The test showed the maximum working frequency of 90MHz for DWT, 140MHz for EBCOT, and 6.75mW/MHz of the total power consumption. THJ2K can process 12 frames per second for the image with resolution of 1280x1024x24bits (YUV422 full color)...