FPGA Implementation For Image Compression System Based On JPEG2000

Compared with former image compression algorithms, JPEG2000 has characteristics of higher quality and more new features under the same compression rate condition. But on the other hand, the computing complexity is also higher, which makes the implementation very difficulty. So, in this paper, we focus on implementation of JPEG2000 based on FPGA platform.In this thesis, the framework of this system is introduced at first. Then, due to the redundancies of data in EBCOT scanning process, we have to adopt skipping methods to ignore the data that are not required when coding. Some of algorithms are presented firstly, and after analysis and comparing, we combine and propose the unique method. The detailed designs of wavelet transform based on FPGA are also presented in this paper. We form a general model of interface between FPGA and RAM by abstracting from our system. And we test the performance in timing. The simulation results show that different constrains could make the system different in timing performance. We impose the optimal constrains to get the finest results, which make the system can work under higher clock frequency.In the rate control algorithm recommended by JPEG2000, All the bits need to be coded in the rate distortion module of JPEG2000 to get the optimized truncated point. Although, the distortion can be lowest, the time consumption is too much to implement in real-time system for high resolution images. An improved algorithm is proposed to reduce the time consumption of JPEG2000 by obtaining the truncated point in the process of the coding. With this algorithm, not all of the bits are coded. The time consumption is greatly reduced and the performance of image is nearly not changed.