The Implementation Of Multi-Rate Digital Signal Up-Converter And Down-converter Based On FPGA

With the development of the Digital Signal Processing, Signal Processing, Coding,Transmission, Storage and other workload increases.In order to save computationaleffort and storage space in the signal processing system, different sampling rates, aswell as conversions amongst these signals will be utilized. Consequently, multi-ratedigital processing comes out and develops. The Up-conversion and theDown-conversion (DUC, DDC) becomes one of the key technologies for the wirelesscommunication. The goal of this thesis focuses on the FPGA design andimplementation of the Multi-rate Digital Frequency Converter in physical layer, basedon Wimax IEEE802.16e protocol of Wireless Communication Networks.Firstly, the thesis introduces the basic knowledge and algorithms of the Multi-rateDigital Signal Processing, Up-converter, Down-converter. The design and optimizationof The Frequency Converter is based on the system requirements. The design of TheDigital Oscillator (NCO) is based on the CORDIC Algorithm. The design ofFrequency Converter adopts the cascade of the CIC Filter and The FIR filter. CIC filteris implemented by the technology of multi-interpolation and multi-decimation. TheFIR filter is implemented to be a pre-compensation filter or a compensation filter basedon the Distributed Algorithm (DA). The correctness of various modules of theFrequency Converter is verified by simulation for each module. And compared withthe results of Matlab simulation platform, the functional correctness of the FrequencyConverter is further proved. For Up-conversion module, considering the systembandwidth is16MHz, input signal frequency is17.92MHz,6times of the up-samplingfiltering, which results in the output signal frequency achieving107.52MHz andrealizing the target of the high-speed signal transmission. For Down-Conversionmodule, the higher rate transmission signal can be converted into a lower rate basebandsignal by the meaning of decimation, which results in achieving the target of dataprocessing at the lower frequency. Finally, the thesis introduces the implementation ofthe Up-converter and the Down-converter with Arria GX90EF1152I6FPGA.