Research On Hash Unit In Fast Bus Interface Based On Network Processor

With the development of Internet and technology, people have a big demands onthe speed of network and its flexibility. To meet these requirements, solutions fornetwork processor have been proposed. Network processor is a new type of networkequipment, on the one hand, it has the advantage of ASIC, on the other hand, it hasthe flexibility advantages of CPU-based network equipment.Hash unit is a hardware module in network processor and provides the hardwareindex of hash index. It has important applications in both address filter and networkdistribution. This paper based on the research of high-performance network processor,fast bus interface and hash unit implemented by hardware are analyzed andresearched. Firstly, three methods for hardware implementations of hash index arediscussed: Directly selected some certain bits of the address, hashing using XORfolding, and hashing using CRC. Hashing using CRC provides relatively betterresults in the three methods. However, it has large hash-collision in some cases. Thispaper, propose a new methods to provide hardware hash index, based on CRC, whichcan adjust parameters (by register values), to adapt some of the bad situation of thehash index. This hardware structure of hash can improve the flexibility apparently.Then discusses the engineering implement method, propose establish a look-up table.The whole design and RTL level description are completed with VerilogHDL,and functional verification is also accomplished compared with the results inModelsim and SDK. At last, the synthesis optimization of the design is discussedwith Xilinx ISE. The results show that the design of the hash unit can achieve theminimum clock period is6.645ns, and the maximum frequency can reach150.480MHZ, which can meet the system requirements for the frequency.