Research And Design Of General Accelerate Unit For Hash Function

The hash function plays an important role in cryptography,which is widely used in trusted computing and identity authentication,etc.For different security requirements under different application scenarios and the problem of low performance in general-purpose processor.For different security requirements under different application scenarios and the problem of low performance in general-purpose processor.Extracting subgraphs to generate custom instructions based on the sample hash algorithm.And a reconfigurable unit for hash function with its fusion architecture is designed to improve processing performance.The main work and research results of this paper are summarized as follows:A custom instruction generation method based on directed acyclic graph(DAG)is proposed.First,we generate the DAG of sample algorithms by LLVM compiler and use pruning operation to reduce the search space.Through the subgraph searching algorithm based on genetic algorithm,the maximum subgraph grown by a single node under constraint conditions is taken as the population individual.The optimal candidate subgraph set can be obtained within the polynomial time complexity after a certain times of evolution through bio-inspired operators including selection,crossover and mutation that starts from a population of randomly generated individuals.We also propose a quantitative evaluation method of subgraphs based on the parameters including delay,frequency,performance benefits and the number of sample applications using the instruction,thus achieving a comprehensive quantitative measurement of the quality of candidate subgraphs.In that way,all candidate subgraphs can be sorted by their quality value.It can ensure that the subgraphs with good compatibility can get higher scores,the ones with high usage rate in single algorithm also won’t be ignored.In this paper,subgraphs are selected in the way of the dynamic programming.By determining the state variables,decision variables and Bellman equation,we can make the selected subgraphs achieve the optimal performance acceleration ratio,and provide data support for the hardware design of reconfigurable units.In order to generate custom instructions for the design of the acceleration unit.We design the parameters by studying the structure of the control and data flow graph of sample hash function.According to the subgraph mapping rules,the selected custom instructions are mapped into the basic structure,obtaining the acceleration unit for hash function.We then design and optimize the interconnection.Under the premise of meeting the functional requirements of the reconfigurable unit,the sparse interconnect we designed can further reduced the area and the average power consumption.A fusion architecture of acceleration unit is also designed.By optimizing the pipeline of baseline processor,the acceleration unit can be connected with the baseline processor tightly.We designed the instruction format of custom instruction.The baseline processor can distinguish the basic instruction and custom instruction by adding the identification bit.The configuration of the acceleration unit is implemented by the configuration information RAM.The operating mechanism of the acceleration unit is designed so that the fusion architecture can realize the normal execution of the custom instructions without destroying the pipeline.The functional correctness of the reconfigurable unit is verified,and the logic synthesis is realized based on the 65 nm CMOS process library to evaluate the performance of the acceleration unit.The mapping of the algorithm on the acceleration unit is completed for typical hash functions.The experimental results show that the acceleration unit designed in this paper can not only improve the performance of the sample hash function,but also accelerates the implementing of non-sample hash function.It has high acceleration performance and good compatibility.