The Design And Implementation Of Address-Data Flow Unit In FT-C55LP

FT-C55LP is a 16-bit fix-point low-power DSP. It has super Harvard architecture, which is consisted of five data buses and one program bus. The pipeline is 12 stages deep, and the resource conflict is completely resolved by hardware mechanism. For the purpose of the efficacious use of the hardware, FT-C55LP designed an Address-Data Flow Unit (A-Unit) which contains a Data Address Generation unit (DAGEN) and an auxiliary ALU designedly. The existence of this unit enhances the data processing ability of FT-C55LP greatly. In this paper, A-Unit is designed and implemented with the top-down methodology, basing on thorough research of FT-C55LP instruction system and micro-architecture.DAGEN generates data address of instructions which have memory access operations. It's a prerequisite of the well functional pipeline. Its implementation relies on the addressing modes of FT-C55LP. In this paper, we firstly analyze the typical arithmetic of DSP and then we discuss the reason and the benefit of the special addressing modes in DSP. Based on this, we design the addressing modes in FT-C55LP and the hardware of DAGEN. There are three units in DAGEN, and they can execute three memory read operations or two memory write operations per cycle at most. We design the reusing-hardware and the rules for parallel use of the hardware by instructions, which are all based on ingenerate ILPs of the instruction set. These design methods can reduce the power consumption of the system.The reason we design the auxiliary ALU based on two following facts. First, the TI C5410 DSP, which doesn't have auxiliary ALU, has many conversion operations from 40-bit to 16-bit. Second, DAGEN supports two instructions issu per cycle. This ALU operates 16-bit registers in A Unit mostly. So it is also designed in A Unit. We design and inplement the hardware of this ALU based on its fuctions. Some simple operations can be performed by this ALU when the primary ALU is running or be dispatched to the low power ALU—auxiliary ALU. So the existence of the auxiliary ALU enhances the parallel of the instruction set and reduces the power consumption of the system.At the end of this paper, the verification involving module and unit of our design is performed and we statistics the code coverage at the same time. The results of simulation show that our design can fully meet the technical requirements of FT-C55LP, and the function is correct.