The Functional Unit Design Of Multimedia Application Specified High Performance DSP Processor

Multimedia processing such as real-time compression and decompression of audio and video is now expected to be the driving force in the evolution of both microprocessors and DSP's. Multimedia processing requires media processor architecture optimized to run multimedia applications and lead to high performance, low power consumption. For that reason, a RISC/DSP architecture media processor-MD32 has been developed.The main aim of this thesis is to study the structure design of high speed function units in MD32 chip using DSM (Deep Sub-Micro) technology. And some low power considerations in data path design and on-chip memories design have also been taken.The MAC operation is essential to media processing. A MAC unit has been specially optimized and can complete a 32-bit MAC operation within one clock cycle of 5ns. We analyze the multiplication procedures and find out the obstacles to improve the speed. To accelerate the multiplication operation, a modified Booth structure has been used to reduce the number of partial products. And Wallace tree structure with LRCF (Left-to-Right, Carry Free) algorithm has been applied to make the addition of partial products and carry propagation in parallel. The ALU of MD32 has complex functionality because of their supports for multimedia extension instructions. A split ALU structure has been used to accomplish the SIMD operation and achieve high speed operation. In the RTL level design phase, we apply 3 methods to improve the speed of ALU unit and DAG (Data Address Generation unit) which support the bit-reserve addressing and circular addressing:1. Analyze the critical path of the critical module, find out the most important signal that causes the delay of this timing path, try to modify the structure and improve the speed of the unit.2. Using the DFG with operation delay and wire delay information to analyze the complicated MUX structure, partition the critical MUX operation, regulate the structure, to improve the speed.3. Using pipeline technique to accomplish the most important operation in more than one stage, such as SAD, which could not be finish in one pipeline stage at any cost.The on-chip memories and data path usually consume most percentage of power in media processor chip. To reduce the power consumption of cache, sub-bank technique and Read/Write Buffer technique have been considered. To improve the energy efficiency of data path unit, clock gating technique has been applied. Both of them achieve satisfactory results.