The Design And Implementation Of1GHz Address Generation Unit In X-DSP

X-DSP chip is a32-bit high-performance DSP chip with a VLIW structure and1GHz main frequency. Address generation unit is an essential kernel components ofvarious types of DSP chip．This chip is a top-down design which is indepedentlydeveloped by our university. Address generation unit designed and realized in thisarticle is the essential component of this X-DSP chip, used for data address calculationand generation.This article conducts comprehensively logic design and verification of this addressgeneration unit, and completes logic synthesis and optimization based on45nm CMOStechnology. Besides, it also completes physical design of this component based onsemi-custom hand-made physical design process. The main content and results of thisarticle are as follows:1) According to the design demands of this address generation unit, design theoverall structure of this component is designed, and the detailed design of eachfunctional module is completed.2) Adder is the core calculation module of this address generation unit, and is inthe critical paths of address calculation and arithmetic operation. This article designsand realizes a high-speed32-bit improved Sparse Tree Adder, which solves the delay ofthis critical path.3) This thesis realizes a structure that can finish cyclic boundary overflowadjustment rapidly. Thus it solves the problem of cycle address generation in circularaddressing mode.4) Nonaligned Memory Access is a design challenge of this address generation unit.This article achieves an efficient Nonaligned Memory Access address calculationstructure. In this way, it solves problem of address generation when accessing datablock across the border in circular addressing mode.5) Logic simulation and FPGA verification platform of this component areconstructed, and comprehensive system-level verification of the designed component iscarried out. The verification results show that this component fully meets therequirement of design functions. The high code coverage rate also indicates thesufficiency of the verification.6) With the application of45nmCMOS technology and DC synthesis tool ofSynopsys Company, the comprehensive results show that: the working clock cycle ofthe address generation unit reaches the design goal of0.7ns.7) The custom layout design of the entire address generation unit is completed bythe method of semi-custom hand-made physical design. Layout analysis resultsdemonstrate that: the final working frequency of the designed unit reaches the design goal of1GHz.