Compiler Design And Optimization For Coarse-grained Reconfigurable Security Chips

With the continuous development of information technology,cryptographic chips play a crucial role in ensuring information security.Coarse-Grained Reconfigurable Architecture(CGRA)is a new programmable logic device with both flexibility and high performance.Its internal circuits can be dynamically reconfigured according to the needs of algorithms to meet the various needs of users.Static configuration has the advantage of smaller task scheduling resource overhead,and it is often used in the configuration of periodic tasks,especially in algorithm applications with cycle-intensive computing.Most computing-intensive algorithms contain a variety of if-else branch structures,especially cryptographic security algorithms have the characteristics of multi-branch structure,multi-loop,and large amount of calculation.Therefore,the handling of branch structures is a major challenge in the design of current information security-oriented CGRA compilers.The existing branch structure processing technology mainly includes the full predicate technology and the partial predicate technology.Since the conservative longest initiation interval(II)is used as the waiting time between two adjacent loops,the scheduling and mapping process has the disadvantages of long compilation time and poor performance when dealing with branch structure of cryptographic algorithm.Aiming at the irregular branch structure in cryptographic algorithms,this thesis proposes an optimized processing scheme for Dynamic Initiation Interval Pipeline(Dynamic II Pipeline,DIP).This scheme separates the long and short paths of the map by duplicating the short paths,and constructs two pipelines with different IIs,which effectively accelerates the cycle of the irregular branch structure in the cryptographic algorithm,and has the advantages of short execution time and fast iteration speed.In addition,the cryptographic algorithm contains many multi-fan-out nodes in the map structure.For such nodes,this thesis optimizes the mapping scheme by inserting blank operators,making full use of the parallel computing capability of reconfigurable units,and adopts the pipeline design scheme,which saves a lot of hardware resources and improves the computing performance.The final experimental results show that,compared with the existing mapping scheme,the design of this thesis improves the computational performance of the mainstream cryptographic algorithm by 38.62% on average,and the compilation time is shortened by 29.9% on average.The research results of this thesis will further shorten the algorithm development cycle,save the mapping process of manual configuration algorithm,and avoid the problem of inconsistent mapping results caused by the difference of layout and wiring.Therefore,the calculation performance of manual mapping algorithm is used as the comparison object in this thesis,and the mapping performance of compiler reaches 87.81% of manual mapping performance on average.