The Analysis And Design Of High-Stability480MHz PLL For USB2.0

USB2.0interface standard gains great popularity due to its advantage inincreasing the data rate between two equipments up to480Mbps.Nowadays, there are two specifications of USB2.0products on themarket: Full-speed and High-speed. The theoretical maximum data rate ofHigh-speed is480Mbps. To make sure the consumer’s equipment canstably transmit data at the high speed, this paper proposes an analysis anddesign of a high-stability480MHz PLL for a stable and accuracy clock inthe PHY MAC part of USB.This paper firstly introduces the basic principles and structures of PLLand stresses charge pump PLL which is adopted in this paper. At first, theprinciples, the structure of circuit, mathematical model and transmissionfunction of modules constituting a CP-PLL，like PFD，charge pump，loopfilter，VCO and frequency divider, are given. Then, loop analysis isperformed on PLL on system level, including open-loop and closed-looptransmission function, the distribution of zeros and poles, frequency response and noise model.The design of a high-stability480MHz PLL is proposed in this paperbased on the analysis above. The design method and circuit is givenrespectively in the sequence of module, then simulation and analysis areperformed on the designed circuits. In the design, VCO is implementedusing four-stage difference ring oscillator and loop filter is implementedusing two-order passive RC loop filter. In addition, this paper proposesthe circuit design of a current adjustable charge pump which contains twoparts. One component is supposed to adjust the current of charge pump;the other is the switch of charge pump. In the former part, to enhance theratio of superior products and compensate the deviation of the circuitparameters results from the dispersal during technique fabricationprocedure, the stability of PLL is greatly improved by changing the setupof external control signal to regulate the current. The amplitude of thecurrent of traditional charge pump circuit is constant, or can only bechanged by adjusting the width of current mirror MOSFET. If the currentof charge pump is fixed, the frequency of PLL varies by adjusting loopfilter or VCO. However, it greatly changes the transmission function ofthe whole PLL and is not good for controlling the whole loop; if theamplitude of the current got changed by adjusting the width of currentmirror MOSFET, the change of the amplitude of the current often involves the revision of layout. In this paper, our charge pump featuresgreat flexibility when realize decimal times current by adjusting controlsignal bit. In the latter part, boot-strapping circuit is utilized. Afteranalyzing the non-ideal factor of our charge pump and comparing it withthat of other two basic single-port charge pump, we concluded that thecharge pump proposed in this paper effectively solves the problem ofcharge sharing, and leads to more suited up current and down current,which results in an enhancement of the stability of PLL.To achieve even higher stability, the PLL circuit in this paper gotoptimized by regulating the parameters of loop filter, aiming at the effectsof loop filter on bandwidth based on the system-level analysis of PLL.Then, when compared with the result of simulation, PLL features a largerphase abundance ratio and a larger SNR, locating bandwidth at areasonable place for noise and lock time equalization, Vctrlrepresentingstable frequency in time domain is more stable. USB2.0High-speed aftertapeout operates properly and PLL proposed in this paper reaches therequirements.