The Design Of H.264 Video Coder Of Intra Prediction System Based On FPGA

H.264 video codec standard has the merits of high compression ratio, high image quality, good network compatibility and so on. It has a widespread application in digital television broadcast, network streaming multimedia, real-time video communication and other various aspects. Improving the speed of H.264 intra prediction is very important for the places of high real-time requirements. As computing complexity and real-time of the software implement of H.264 intra prediction is the major processing bottleneck. Therefore, based on the related researches, a parallel and pipeline implementation of Intra prediction algorithm based on FPGA is proposed in this paper.The paper discusses the H.264 Intra prediction technique. By analyzing all kinds of intra prediction mode algorithm, Matlab simulation model is used to demonstrate all kinds of intra prediction mode in both luminance and chrominance. And the paper tests and compares the affection on the prediction performance of prediction modes on the JM12.2 platform. According to the test result, some of intra prediction modes are cut: Then the design of intra prediction system based on FPGA is proposed. By color transform module, RGB pictures gathered the front module are transformed YCbCr pictures. Control unit stores YCbCr pictures to SDRAM, reads and writes the data to intra prediction module. A parallel reconfigurable intra predictor generator is proposed in intra prediction module. The circuit structure calculation predictors between different prediction modes and reduces the computing complexity. In the paper, the hardware architecture of multi-modes parallel processing units is proposed. By using nine-parallel processing units with the same structure, the module calculate the sum of absolute transform differences (SATD) value for each kind of intra prediction. The 2D Hadamard transform can be divided into two 1D transforms which can be implemented with butterfly operations. The design uses the methods of fast algorithm and pipeline processing to enhance the hardware processing capabilities. At last, a LCD display module is designed to show the best prediction mode.The intra prediction system is divided into some function modules by using the design approach of hierarchy and modularization; Pipeline and ping-pong operation is used to increase the parallelism, speed and bus utilization rate of the system. All of the modules are designed using Verilog, simulated in Modelsim, synthesized in ISE9.1 and verified to work at 106.7MHz. The result indicates the design meets the real-time requirement. The paper carries out a good research for H.264 video compression coding system based on FPGA and it provides a degree of application value.