H.264 Intra Prediction Algorithm Optimization And Several Important Module Fpga Implementation

As the new generation of video compression standard, H.264 can reduce 64% bitrates on average at the same picture quality as MPEG-2 which is the last generation video compression standard. H.264 only specifies the syntax framework of the bitstream and the decoder architecture. With the flexiable implementation, H.264 has three profiles that support different function to meet different requirements.H.264 has great capability of compression, but it's much complexer than others.This paper analyses the complexity of H.264 encoder and its pivotal arithmetics.H.264 adopts a new intra-prediction arithmetic.To improve the video compression quality and bring down bitrates, H.264 adopts the RDO arithmetic.It needs to calculate the RD-cost value for 592 times to get the best intra-prediction mode of a Macroblock. In order to reduce the complexity, this paper proposes a fast arithmetic for intra-prediction mode selection.Many times experiments prove that: it can reduce more than 60% calculated time on average by using this new arithmetic with little loss of PSNR than the primary arithmetic.Considering the real-time encoding and the flexibility of FPGA, this paper put another focus on implementing the baseline profile of H.264 encoder by FPGA.First of all,a hardware architecture of the encoder has been proposed.Then we have studied the most important modules of the encoder which influence the efficiency of encoding and implement them separately by FPGA.In this paper, integer DCT,quantization,Zig-zag scan , CAVLC,inverse integer DCT and inverse quantization etc have been studied and implemented by FPGA.In the end of the paper, simulation and test for the whole system have been complished and it proves that it can encode residual data real time.This paper has improved the intra-prediction mode selection arithmetic of H.264 which is easily been implemented, and it is useful for real time encoding. The research for implementation of H.264 encoder by FPGA is a new attempt and it is useful for reference of CMOS chip design for H.264 encoder.