Design Of Intra Prediction And Inter Prediction In H.264 Based On FPGA

H.264/AVC is the newest video coding standard, which is jointly established by ITU-T and ISO. There are many advantages in H.264 such as high compression ratio, high image quality, excellent network compatibility and so on. It is applied in more and more widespread field such as digital television broadcast, real-time video communication, network video streaming transmission, multimedia message and other various aspects. At present, Hardware realization has become the hot spot for H.264 encoder. Intra prediction and inter prediction are the critical modules for H.264 encoder of high compression ratio and quality. In order to match the request of resource cost and real time in H.264 encoder IP core, the intra and inter prediction module are mainly designed for hardware implement in the paper.In depth study of the H.264 video compression principle and considering of the characteristics of FPGA and SOPC, the paper presents a H.264 video encoding system framework based on SOPC. In order to design for hardware realization, the algorithms of intra and inter prediction are improved rationally. The paper also accomplishes the hardware design of intra prediction and motion estimation modules.The paper mainly includes the following contents:1. The paper deeply studies the critical technologies of H.264 video compression and presents one H.264 encoding system framework based on SOPC combining the characteristics of SOPC and pipelining .2. The paper designs the intra prediction module in H.264 encoding system. After analysing in depth the principle of intra prediction, one unified computing model is put to use to complete all of the prediction modes. And also a 4-way parallel configurable structure is presented to speed up the process. This structure balances between the processing speed and the hardware cost, thus its hardware implementation efficency is very high.3. The paper designs the inter prediction module in H.264 encoding system. After analysis and comparison on various motion estimation algorithms, hierarchical full search algorithm which balances beween the hardware complexity and performance is used. Through parallel and pipelining processing, the structure for FPGA realization is designed and the dataflow is analysed in succession. The search array is designed making full use of data reusability. After that, each sub-module of motion estimation module is designed in detail. The number of PE is fewer than that of other structure on the premise of guaranteeing the search performance and the hardware cost is reduced greatly.The results of simulation and test show that: in this paper, the design of the intra prediction module and motion estimation module have advantages and banlances well between the efficiency and the hardware cost. The paper supplies a degree of application value for H.264 video compression coding system based on FPGA.