Research And Design Of Reconfigurable IU

This paper present a design method of IU, which use the reconfigurable technology. In the design, priority is given to the power consumption of the microprocessor chip and the size of the integer unit, we design these computing components: arithmetic logic unit (ALU), parallel multiplier, a roller shifter, parallel divider.In the ALU, we integrate the method of equinoctial node-group and conditional sum adder to design reconfigurable ALU, and join negative logic circuit design design principle into it. In the barrel shifter, the relevant shift operations are achieved at the basis of 64 bits barrel shifter by the control of external control circuit. In the design of the multiplier ,we use the parallel multiplier structure of MBA-WT(Modified Booth Algorithm, MBA;Wallace Tree, WT), and use 4-2 compressor to achieve WT structure, avoiding the use of ordinary 3-2 compressor causing cabling complexity.In the design of divider, we design a the non-resorting algorithm divider that can compute two bits quotient in one time, in conjunction with the advantages of divider of using the non-resorting algorithm and high-end divider.