Research On Test Data Recombination Technique For Optimizing SoC Test Performance

Along with the continuous improvements in the semiconductor manufacturingtechnology, the integrated circuit is becoming more and more complex, andmillions of transistors can be integrated into a silicon die. However, testing SoC isvery costly due to increase in test data volume, test power consumption and thedifficulty of accessing cores embedded in it. Test resource partition (TRP) is one ofmain optimization techniques, which includes test data compression (TDC), designfor testability (DFT) and test scheduling. Aiming to optimize SoC test performance,this thesis does research on TRP technology based on the prior work. The maincontributions include presenting a core test pattern recombination technique forreducing test power consumption with high compression ratio and proposing amulti-core test data share and test scheduling technology to implement a multi-coreconcurrent test method for effectively reducing SoC test application time.The research on expended pattern run length shows that ignoring bits withdifferent values will affect the compatibility of patterns, ultimately changing thecompression ratio. To solve this problem, we proposed a test pattern reordertechnology. Starting with dividing the scan chains into a group of scan slices basedon pattern length then calculating the compatibility between patterns correspondedon scan slices. The patterns are reordered according to the probability of thecompatibility. At the same time scan slices will be reordered according to the orderof patterns. And multiple scan chains architecture will be adopted. The proposedscheme is applied to the MinTest set, test data compression and shift power will beassessed. The experimental results show that the proposed scheme can effectivelyreduce the shift power and ensures a high test data compression.This thesis explores a concurrent test method for multiple cores to reduce SoCtest application time. By pre-treating the test sets and analyzing the compatibilitybetween test vectors in multiple core sets, the compatible patterns will be mergedinto a shared test set, which is broadcasted to every core under test during test. Abus control unit is designed to apply core test data, multiple cores being testedconcurrently. The experimental result shows that the proposed scheme is useful toimprove data compression rate and reduce test time.