Tsv-Aware And Thermal-Aware Floorplanning Algorithm For3D Chip

With the development and application of VLSI，three-dimensional chip hasbecome one of the fastest growing technologies in the semiconductor industry. It isa new method that can overcome limits of feature size and improve performance.Comparing with the traditional2D chips that all modules are on a flat layer,three-dimensional chips allow multiple integrated chips stacking, TSVs(ThroughSilicon Vias) are used to provide the vertical direction of communication for dies.Three-dimensional (3D) chip is structured by vertically stacked multi-planardevice layers, which is used for vertical interconnection between different layers byTSVs. So it significantly reduces the interconnect length and increases integrationdensity. In further it has lower power consumption and smaller form factor, and itbetter meets the bandwidth requirements. However, series of problems are broughtby three-dimensional chips. For example, a single TSV occupies a relatively largerchip area in terms of the present feature size, and the immaturity of the alignmenttechnique of the TSVs also lowers the yield of the chip, so the introduction of toomany TSVs will increase the cost of chip manufacturing and testing. Verticalstacking makes the chip integration density and the power density in the same areaincrease a lot simultaneously, that makes heat double.For these problems, We studied the floorplanning algorithms for3D chip andproposed a collaborative considered TSV and Thermal Floorplanning (named2TF)algorithm, by which the device power, interconnect power and the number of TSVsare simultaneously considered. The three-dimensional chip floorplanning algorithmis based on a two-stage simulated annealing. In the first stage of the simulatedannealing algorithm all the modules are put into to the appropriate layer. By sixdifferent disturbance operation, the algorithm synchronously minimizes the chiparea, the wire length and the TSV number to make modules with higher powerdensity be evenly divided into different chip layers. In the second stage ofsimulated annealing, the results of the first stage of floorplanning are used as theinput of the the second stage. It uses four layer disturbances operation separately toadjust floorplanning for each layer of the chip to further minimize chip area andtotal interconnect length, and synchronously to reduce the peak temperature of the chip. The experimental results on the MCNC benchmark circuits showed that thenumber of TSVs had a greater reduction and the peak temperature of the chip hadhuge improvement. It can be used to guide the design of more low-cost, low powerconsumption, and high-performance3D chips.