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Thermodynamics Research Of TSV Based Three-dimensional Chip

Posted on:2019-12-01Degree:MasterType:Thesis
Country:ChinaCandidate:G X ChenFull Text:PDF
GTID:2428330563992277Subject:Software engineering
Abstract/Summary:PDF Full Text Request
When the traditional two-dimensional integration encountered the bottleneck of the physical limitations during the process of increasing the integration rate,the high-density three-dimensional chip packaging technology has become a important technical way in the integration of microelectronic circuit-level.Through-Silicon-Via(TSV)technology is one of the most promising next-generation integrated packaging technology between chips and chips,wafers and wafers and has been rapidly developed in recent years.However,the vertical three-dimensional TSV chip is facing the problem of thermal management.Since the vertical TSVs are usually filled with materials with high thermal conductivity and thermal expansion rate,such as metallic copper,the rise of temperature can be obvious.At the same time,the problem of thermal expansion caused by temperature change can not be neglected when the temperature is raised.The thermal expansion coefficients of different materials do not match,which will cause the thermal stress that can even destroy the device structure in severe condition,making the device failure.Therefore,with the decrease of device size,the impact of thermal management can not be ignored.In this paper,we have designed a three-dimensional chip package structure based on vertical through silicon vias.Based on the finite element principle,the finite element analysis software ANSYS was used to build the three-dimensional model of the structural unit,and its structure parameters were changed to perform a series of electrothermal simulation and thermal stress simulation.The effects of different structural parameters(including chip thickness,TSV pitch,TSV depth,TSV shape,etc.)on the thermal stress distribution and thermal effects of the device are analyzed.Based on the results,chip thermal management analysis and reliability analysis are being designed,a model has been established and a reliable solution is given.In addition,this paper also proposed a suitable filler for the TSV chip,Diamond / Cu composite material,this material has a high thermal conductivity low thermal expansion while maintaining the characteristics of high conductivity,which has a significant role on TSV chip to reduce the thermal stress.Finally,the reliability of the three-dimensional chip under industrial environment is analyzed.By comparing the thermal effects and thermal distribution characteristics of the TSV chips under different conditions,the thermal stress state and deformation characteristics of the thermal reliability of structural materials TSV Chip under different temperature conditions are compared with the actual industry condition.
Keywords/Search Tags:3D packaging, Through Silicon Via, Thermal effect, Thermal Mechanical Stress, Reliability, Finite Element Analysis
PDF Full Text Request
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