Three-dimensional Integration Thermal Management And Chip-level Thermal Stress Modeling And Simulation

Under increasing demand of miniaturization and low power consumption of electronic products,the three-dimensional stacked chips based on through silicon via(TSV)has emerged at the historic moment.In three-dimensional integrated circuits(3D ICs),the silicon interposer can connect and carry many chips to realize the expansion of similar chips or the high-density integration of multiple functional chips.But 3D ICs still face many problems and challenges,the wafer stacking method of 3D ICs increases the number of cores in a package.Under the influence of thermo stress,it is more likely to cause serious thermal reliability problems.This article proposes an effective heat dissipation method and clarify the distribution of thermal stress and possible failures in 3D IC.The finite element analysis(FEA)is widely recognized as a reliable analysis method.When dealing with the simulation of large-scale circuits in 3D ICs,FEA often encounters the situation where the simulation time is too long or even cannot run due to the limitation of the simulation environment.Therefore,the convenient thermal analysis model and the thermo-mechanical coupling analysis of the system have great significance and promising prospects for the further development of 3D ICs.This article focuses on the research work of 3D ICs thermal management:The thermal redistribution layer(TRDL)and thermal TSV(TTSV)are used to build a heat dissipation structure applied to 3D ICs.The heat dissipation structure comprehensively considers the horizontal and vertical diffusion of heat to improve dissipation efficiency.The comparison results of FEA show that the maximum temperature drops by 4.43? after adding TRDL.Compared with FEA,heat flow analysis(HFA)with Fourier heat flow analysis theory greatly shortens the time of modeling and simulation.The single simulation time can be shortened from more than ten hours to a few seconds by HFA,which improves the efficiency of thermal analysis.The maximum error of the simulation results between HFA results and FEA results is 2.98%,the reliability of the HFA results is verified by the FEA.Compared with traditional 2D ICs,the structures of stacking and TSV will increase the impact of thermal stress in 3D ICs.This article designs the layout of a silicon interposer for heterogeneous integration and imports its structural model from ECAD software into ANSYS workbench for thermal stress analysis.The influence of wiring density,solder ball size,TSV layout,and large-area copper of power ground on the thermal stress of the chip are obtained by FEA,which can provide a reference for layout design.Thereby improving the yield rate and reducing the design cost.In this paper,the thermal stress analysis of the Chip-Interposer-PCB assembly structure(Chip-Interposer-PCB,CIP)is also carried out.According to the simulation results,the solder balls that are more likely to be separated are obtained.When assigning signal lines to solder balls,avoiding high-risk solder balls to reduce the risk of failure.