Research On Decoding Algorithms For LDGC Codes And FPGA Implementation

Under the backdrop of dramatic increase in the current communication business, thedemands of validity and reliability of the communication system had been further enhance. Thechannel coding techniques are an important means to solve the information loss in the process ofchannel transmission during communication system. The LDPC Codes has a good channelcoding performance near the Shannon limit. It can be widely used in communication systems anddigital storage systems. Thus it is a hot topic research on implementation about LDPC Codes,moreover the research has a great practical significance.Firstly, this thesis has a brief introduction on the H matrix constructed and LDPC Codesencoding. Then several soft-decision decoding algorithms about QC-LDPC Codes are detailedpresented, and simulated in the Matlab. Finally select the Offset Min-Sum algorithms as thisthesis’s algorithm. And some parameters of this algorithm such as the maximum number ofiterations, the offset number and the data width of quantization are decided by simulation.Secondly, implement the Offset Min-Sum algorithm based on the FPGA of Xilinx Vertex-IIPro series. Particular describe of each function module design and mainly timing simulationdiagram. Then implement them by ISE10.1, and analyzed the performance of algorithm fromsynthesis report. The result shows it meet the design requirements.Finally, set up a SoC test platform for LDPC Decoder by Xilinx EDK. Through the serialport, transmit the data that encoded by PC to SoC test system to decoding. And then the decodedata back to PC through serial port. Lastly, analyzed the bit error rate by comparing the originaldata with decode data.