Research On LDPC Code Based On FPGA And Design Of Decoder

LDPC code (Low Density Parity Check Code) is a kind of the linear block codebased on the sparse parity check matrix. It was proposed by Robert G. Gallager in1963.LDPC code overcomes the shortcomings of the other codes, which has the excellentproperties of approaching shannon limit and advantages of low decoding complexity andflexible structure. Since it was rediscovered in1990s, it has become a hot spot in the areaof the channel encoding and decoding after Turbo codes. LDPC code is widely used indeep space communications, satellite communications, optical communications andsatellite digital videos. And it has been a powerful competitor in the upcoming fourthgeneration mobile communication system.Firstly, the paper made a brief introduction about the digital communication systemand the knowledge of channel coding theory, and then provided a definition of LDPCcode, followed by a detailed study about the LDPC code representation methods andconstructing methods.Secondly, the paper studied the LDPC code decoding algorithm, which included thehard decision decoding algorithm and soft decision decoding algorithm. This paperfocused on the research of the soft decision decoding algorithm of BP algorithm andLLR-BP decoding algorithm. And the paper proposed an improved LLR-BP decodingalgorithm, which has been proved that the performance improved significantly comparedto LLR-BP decoding algorithm.Thirdly, in this paper, an improved LLR-BP decoding algorithm is implemented inhardware design, using LDPC decoder design based on top-down design approach. Wegave a more detailed diagram of its implementation and the decoding function module,and used the Quartus II platform integrating various modules into a complete decoder.Then the decoder’s design was verified through comprehensive compilation, functionaland timing simulation. Lastly, we summarized the researched work, pointed out the inadequacies of thepaper and pointed out the next research direction about LDPC code.