Research And Implementation Of Image Processing Techniques Based On Multi-core Processors

At present, with the rapid development of image processing technology, theprocessing capacity of a single processor core has been unable to meet therequirement of timeliness and performance of the high resolution pictures. Andthen as the representative technology of the multi-core processing technology, theNoC (Network-on-Chip) has been the mainstream direction of a multi-core researchin the morden. The multi-core NoC system can communicate and calculatesimultaneously with more than one resource computing nodes, which uses as asimilar way as the communication network, so it achieves the parallelcommunication and parallel computation very efficiently. Therefore, the multi-coretechnology which is based on NoC has bring an effective solution for high speedand high resolution images processing. In this paper, we set up the NoC decodingexperiment platform which is based on on a two-dimensional grid topologicalarchitecture, and then basing on this platform, we design and complete theexperiment work of multi-core JPEG decoding, and though downloading the FPGA,the result verifies the correctness of the design.The main work of this thesis is as follows:1. Comparing the several common topology structures of network-on-chip, andaccording to this paper’s application object, we finally designed a3*3network-on-chip system which is based on the two-dimensional grid topologyarchitecture. We used route switching as the communication mechanism of thissystem, and in the computing nodes, we connected the IP modules and Nios IIprocesser though using Avalon Bus.2. Introduced the design of the router module, the communication protocol,message format, network interface module and the main module unit of computingnodes. Then taking JPEG as a starting point, we designed two different multi-coreJPEG decoding scheme, and introduced the work flow of NoC system and thehandshake mechanism between the modules of this two schemes.3. According to the design of the hardware architecture and software dividing,though downloading the system on the Altera company’s Stratix II EP2S180FPGAdevelopment board, we achieved the multi-core JPEG decoding experiment and verified the correctness of the design. At the same time, we gave the performanceexperiment parameters of the two kinds of schemes, and made an analysis about theperformance difference reason of this two kinds of schemes.