The Design And Realization Of Heterogenous Multi-core Architecture

In the field of high performance processors,limited by three main factors of power consumption,connectivity and complexity,the growth rate of processores' performace have been unable to meet the Moore's Law,and heterogenous parallelism will be a new way of accelerating.In the field of embedded processors,combined the characteristics of ASIC with DSP,ASIP owns a semi-customized architecture and provides a trade-off balance between power,flexibility and time-to-market.Based on the characteristics of embedded applications,this paper designed and implemented a Multi-cores ASIP processor with heterogenous architecture.Firstly,this paper designed a Multi-cores architecture based on the on chip bus and the shared memory by the deep research on parallel's key technology.This architecture integrates eight RISC processors and a SPARC processor,forming a heterogenous cluster,and different clusters can be mounted on the same bus to achieve extension.To achieve it,the wishbone bus is chosen as the on chip bus,and a multi-port memory with a secondary address index function is used as the shared memory.Secondly,this paper designed and implemented a SIMD parallel processor array consisting of eight RISC processors,and also configured a set of instructions,the shielding ciruit and the adjacent communication circuit,to simplifying the difficulty of parallel algorithm designing.In addition,this paper designed and implemented a streamlined SPARC processor,which supports the window registers and BCC cross complier tool chain.Finally,this paper implemented the heterogenous multi-core processor based on the VLX240T-FF787 FPGA of Virtex-6 series,using the Verilog.This paper also tested and verificated the processor's function using the 5/3 lifing wavelet decomposition algorithm and the FFT algorithm.In addition,this paper also evaluted the parallel performance using the bubble sorting algorithm.