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The Design And Implementation Of The RS Decoder Based On The DVB-C System

Posted on:2013-07-05Degree:MasterType:Thesis
Country:ChinaCandidate:G P LiFull Text:PDF
GTID:2248330374976079Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
RS(Reed-Solomon)code is a kind of nonbinary BCH code.Because of its structure it cancorrect not only random errors but also outburst errors.So it is widely used in manycommunication systems and digital storage equipment,for examples deep-spacecommunication,optical fiber communication,hard disk array,DRAM,CD etc.This article introduced basic theory of error-correcting code based on the DVB-Csystem,the encoding and decoding algorithm of RS code and the design of the multiplier,alsoits improved methods.By truncating the front fifty-one bits of information in the RS(255,239)code,this paper has found the RS(204,188) code based on the DVB-C system,combined theDVB-C system and the theory of error-correcting,deeply study the structure of the multiplier.bit-parallel multiplier is designed using the optimum WDB.Compared to many othercommonly used multiplier structure,this multiplier can not only implement the transitionsbetween the basis simply,but in speed and consumption of resources enjoy a greatadvantage.The encoder and decoder constructed by the multiplier can implement thetransitions between the basis simply,successfully correct random errors within eight,it can notonly ensure its powerful error correction capability,but take account of the system speed.thismethod can reduce the complexity of the multiplier,also for parallel computation,so it canachieve high data throughput.Based the above theoretical basis,using verilog languagedescribe how to encoding and decoding RS code including the multiplier of the finitefields,Syndrome circuit,Belekamp algorithm circuit,Chien search algorithm circuit,the Forneyalgorithm circuit to solve the error value and the implementation of the delay fifo.After many hierarchical modular designs,using the EP3SL340H1152C3chip of theAltera’s Stratix as the hardware to implement the RS decoder and verifying the decodingalgotithm by FPGA.Through the data vector that needed to be corrected as the inputdata,finally successfully correcting the error and play back the picture and meet therequirements of the DVB-C system.
Keywords/Search Tags:DVB-C, RS(204, 188)code, Weakly-Dual-Basis, Belekamp-Massey algorithm
PDF Full Text Request
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