The Design And Implementation Of BCH Code In DVB-T2System

At the sending end based on the DVB-T2system use the channal coding of BCH code and LDPC code cascaded,and in the actual channel has burst interference and noise, what’s more,the transmission BCH code in DVB-T2system is very long,which will generate more error code.But the DVB-T2system require transmission of quasi accurate and can randomly to correct more errors.Then this article analysis and research the problem from three aspects of the decoding algorithm of BCH code, the hardware design and implementation. Several aspects are included in the thesis:First, a generic BCH decoding algorithm are analyzed and compared. The article discusses the hard decision decoding algorithm such as the Euclid algorithm and the ME algorithm, inverse BM iterative algorithm, BM iterative algorithm inverse and inverse serial BM iterative algorithm from the view of implementation. Finally select the BM iterative algorithm of serial and no inverse to complete the decoding of DVB-T2system, not only to avoid the more difficult inverse operation, and it only takes three finite field multiplier will be able to complete the hardware design and implementation, and greatly reduces the complexity of hardware implementation.Secondly, according to the BCH decoding, which has inverse-free serial BM algorithm, after analyzed, conclusions, the article proposed the BCH error correction code decoding hardware design, which is adapted to the parallel processing of the DVB-T2system. The article have a comparison from two aspects of hardware resources and data processing speed. Main the syndrome computation phase of the BCH error correction code decoding one times the idea of parallel computing, which enables the decoder to be completed within one clock times accompanied calculation. In the Chien search stage, in which the article used two times parallel processing method. In this way, the decoder can be completed within one clock twice Qian Search. It is also has completed hardware design and implementation, which is inorder to solve the key equations. Using the BCH error correction code, not only reduce the decoding time of the parallel processing mode, but also by the way of resource sharing, it could reduce the implementation area.Finnally, The programming language is Verilog language,which realizes the BCH coding algorithm,then test the algorithm and FPGA code by testing platform that tests the error correcting capability of BCH code by inserting one or more error code under programming diffrent test case. This paper mainly introduces the process that encoder correctly encode after inserting one or more error code in the BCH code,and shows the corresponding test results and simulation diagram.The simulation and test results show that adopt this topic of the method of BCH encoder can achieve the integrated results for94MHz, greater than the system requirements for the64MHz, can reach DVB-T2system performance requirements.