Design Of A RS-PC Decoder Chip For DVD Applications

Based on the theory of Reed-Solomon (RS) Code and the analysis of DVD specifications and improved from algorithm, VLSI architecture and flow controling, a full-process piplined Errors-and-Erasures correcting Reed-Solomon Product-Code (RS-PC) decoders chip for DVD application is presented. It features full-process pipelined, high-speed decoding, high performance correcting, Errors-and-Erasures correcting, simpleness of control timing, succinctness of circuit implementation, erea efficience, and with good extends capacity. It can correct errors-and-erasures introduced in the process of storage and recovery of DVD data and also can be used as an IP core in the design of DVD servo chip.The main module of the RS-PC decoder chip are two pipelined Errors-and-Erasures correcting RS decoders and a block buffer manager. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm whith Errors-and-Erasures correcting, which reduced the complexity of the design. Based on the methods of modules reuse, the proposed RS decoder are very regular and erea efficienc. Using three stage pipelines, the RS decoder can operate at a rate of 1 byte/clk. Based on a method of 2 demension data rearrange, a high speed and high efficience implementation of DRAM acess is proposed in the design of block buffer manager. Using the block buffer manager with off-chip DRAM, a (182, 172) row RS decoder and a (208, 182) column RS decoder can be pipelined, which double the speed of RS-PC decoder and get a rate of 1 byte/clk.Based on the DVD specifications, the RS-PC decoder chip specification is defined. The C model of RS-PC encoders and decoder is presented for verification the algorithm. The hardware of RS-PC decoder chip is descripted in Verilog HDL, function simulation and timing verification are processed, and then is implememted in a Xilinx FPGA. Through the function simulation and timing verification, the proposed RS-PC decoder meet the expected performance requirement, which gets the rates of one byte per clock, gets the max row error correcting of 4 errors or 9 erasures and the max column error correcting of 9 errors or 15 erasures, gets a data rate 40Mbytes/s interfaced with a 100MHz SDR DRAM,which meet the 12× DVD performance requirement.