| Approaches to testing FPGA interconnect already exist, but no built-in-self-test (BIST) approach yet exists that can allow fault localization and reporting once an FPGA is installed in the field.; This thesis describes a BIST-based FPGA interconnect test scheme that uses the JTAG capabilities of the FPGA for reporting to an external microcontroller. A number of test configurations and vectors have been designed to locate all wire-segment single stuck-at, open, and wired-and/or bridge faults, as well as stuck-at faults in all Configurable Interconnect Points (CIP's) in the interconnect switch matrix. The study presents a two-phase, test and report, testing scheme. In the test phase, a TPG (Test Pattern Generator) applies vectors to groups of WUT's (Wires Under Test) in parallel. WUT outputs are compared to the test vectors in an output response analyzer, and recorded into on-chip Select-RAM. After all results are saved in RAM, a report phase is entered during which test results are formatted and transmitted out the TAP using the boundary scan clock TCK. (Abstract shortened by UMI.)... |
