Verilog HDL Requirement Consistency Verification Tool Based On STM

IC verification has become an important bottleneck in the process of high-performance chip development.Similarly,the verification of FPGA system has the problem of complexity and comprehensiveness.At present,simulation verification and formal verification technology mainly focus on the middle and late stage of system implementation,but fail to play a role in the consistency verification of early design and requirement.The earlier the system verification starts,the lower the correction cost after finding the error.Considering the comprehensiveness of the verification,the verification work should cover the design and implementation process of the digital system as far as possible.Aiming at the early state transition process of FPGA system design,this thesis designs and implements Verilog HDL requirement consistency verification tool based on STM.This thesis first analyzes the current research status of IC verification,and introduces two main technologies:simulation verification and formal verification.Secondly,it introduces the related technology of the system.Then the functional requirement and application architecture of the verification tool are introduced in detail.The tool has a relatively complete design and verification process,which mainly includes:Use RSML^-e to specify the requirement,and establish the formal requirement model for the system module.According to the structural characteristics of Verilog program,it is divided into data definition verification and STM based state transition verification.The Verilog HDL code is generated based on modules.STM is used to display the state transition of Verilog HDL program logic,and the transition under different events is compared with the requirement model,so as to realize the consistency verification of design and requirement.In order to ensure the correctness and reliability of the tool,the function of each part of the tool is tested.Finally,an example is given to illustrate the design verification and code generation ability of the tool.The tool designed in this thesis focuses on the early stage of system design,uses STM to achieve the requirement consistency verification before code writing,and uses specific examples to illustrate the tool's verification capabilities and practical value.The verification method based on STM proposed in this thesis is a supplement to the comprehensiveness of the current verification technology,and has a certain degree of innovation.