Design Of Model-driven Verilog HDL Modeling And Generation Tool

FPGA is widely used in the field of integrated circuit design and heterogeneous computing because of its rich programmable resources.The development of chip design technology brings design scale and complexity increase,along with this is the difficulty of verification sharply rises.It is crucial for FPGA-based digital systems to conducting requirements verification and design verification.Comprehensive verification of the circuit design as early as possible can discover more design problems to shorten the development cycle and improve verification efficiency.Existing verification methods pay more attention to design verification,while ignoring the consistency verification of requirements.This paper designs and implements a model-driven Verilog HDL modeling and generation tool based on the characteristics of requirements verification and design verification.Firstly,this paper analyzes the current research status of FPGA verification and briefly introduces some existing verification tools.After detailed analysis of actual needs,design and implement Verilog HDL modeling and generation tools.This tool contains three core functions: based on Verilog HDL code logic tabular display,syntax review and code generation,and table-based model establishment and verification.In the implementation stage,use code matching technology to match source code and target code,and improve the cosine similarity calculation method used in the technology.To ensure the reliability of this tool,software testing is applied to test the tool in detail.In this process,the verification capabilities of this tool are tested by three sets of different types of sample data.The Verilog HDL modeling and generation tool designed in this paper is dedicated to adding verification in the requirements analysis stage of FPGA development,so as to shorten the verification cycle,and find requirements description problems and design defects in the early stage of design.By comparing the experimental data,the tool's ability to discover potential problems in the early stages of development was verified.At the same time,the state transition table is used to display the Verilog HDL code logic and state transition,which provides new ideas for the research of FPGA-based requirements verification and design verification.