Design And Implementation Of Sonar High-speed Data Flow Transmission Systems

To combat the adverse effects of a shallow water environment, e.g. pronounced bottom and surface reflections,reverberations and human-made noises,modern digital sonar typically employs an increasingly large array of hydrophones in order to achieve sufficient array gain and good spatial resolution. The trend results in large amounts of data and requires high-speed transfer, presenting a real challenge for the signal processing unit of sonar. One method most commonly adopted is discarding the raw data once they are calculated by the real-time signal processing unit. Although the method does reduce the amount of data to be transferred, it has great limitations in pratical applications since the raw data can be very useful, particularly in the stage of system debugging and testing.The existing system design is mostly designed centered around digital signal processors (DSPs), with some supplementary devices or chips implementing data transmission, whose performance usually has to trade off with other processing/control functions.This thesis develops an optimized sonar transmission architecture design and implements relevant software and hardware design and testing. The design is based on the microprocessor system embedded in a Field Programmable Gate Array (FPGA). FPGAs have been widely applied to signal processing realization because of its flexibility to adapt the hardware and software to changing application needs. Coupled with Gigabit Ethernet, the FPGA system can handle high-capacity data flow communication with a remote terminal while doing data processing. Use of Ethernet as an extern bus is due to long distance propagation (～100m) using a cable between sonar electronics and PC data recording system for post processing, while sonar transmission system employs a bus specified in hardware to connect to forwarding system and receive data flow. Thus, the overall throughput limit of a sonar transmission system is determined by the processing speed of both the hardware-specific communication bus and the Gigabit Ethernet.The sonar transmission hardware used in this thesis is a self-designed, compact circuit board, consisting of a Xilinx FPGA, Gigabit Ethernet PHY, dedicated communication bus and memories.The transmission software is built on the microprocessor after adding an embedded OS and a TCP/IP stack. Regarding to a variety of sonar data transmission and storage requirements,the design provides the ability of adding other functionality over software without costly hardware changes, thus leaving a large space for speed-ups improvement.During the past two years, we have succeeded to adopt this transmission system in a multi-beam echo sounder and an Autonomous Underwater Vehicle-based synthetic aperture sonar. On-site testing demonstrates that the system can tranfer data reliably and effectively. Real-time data transfer at approximately 200Mbps has been achieved, enough for the transmission of merged packets of raw signals, bathymetric data or other manipulation information necessary to warrant complete sonar functionalities. The improved transmission system can achive a throughput up to 700Mbps.