0.18 Um Cmos Low Noise Amplifier Circuit And Layout Design

Due to the rapid development in wireless communication and the CMOS technology, the research of RFIC based on CMOS technology becomes hot point now. This thesis designs an LNA which is the key block of a RF receiver. As the first class of a wireless receiver, an LNA must have low noise, reasonable gain, input and output impendence easy matching and low power dissipation. These requirements are closely relative and how to trade off them and optimize them according to the requirement of a system is the difficult point in a LNA design.A LNA is designed in this thesis and applied in the RF front of 2.4G Bluetooth based on CMOS technology. The main work is:Firstly, the basic components, resistors, capacitors, inductors and MOSFET are studied and emphasis is put on the physical characteristics of MOSFET.Secondly, the noise factor, the most important parameter in LNA, is analyzed basing on the noise analysis of MOSFET with theory of two ports.Thirdly, analysis and comparison of the four topologies of LNA have been done, and the inductive source negative feedback topology has been selected while it has the smallest noise among those four topologies, the technology of noise optimization is also discussed in the restriction of power based on the trade-off consideration on a LNA design, and the LNA design based on that technology is realized. In order to perfect the entire performance of the LNA, the cascode structure is selected to raise the isolation and differential structure to increase the linear.Finally, introduce parasitic, matching, and noise isolation which needs to specially pay attention to in RF layout design, while these will affect the performance mainly. The layout of the LNA has been completed.