Deep Sub-micron RF-CMOS Device Physics And Model Research

Nowadays, with the rapid developments of wireless communications market, especially theRFID (Radio Frequency Identification technology), people rushed to carry out research on RFIC(Radio Frequency Integrated Circuits). With the pursuit of SOC (System on Chip), many studies onCMOS process based on silicon have benn done by researchers. CMOS process based on siliconhas attracted many people all the time because of its advantages, such as mature technology indigital integrated circuits, low cost, low power dissipation and so on. CMOS process is inaccordance with Moore’s Law, and developing quickly. The characteristic dimension continues toshrink as the developing of CMOS process, which makes characteristic frequency more than 100GHz, those progresses make researchers to study on RFIC based on CMOS process possible.Circuits simulation is a necessary method for RFIC design. The success rate of RFIC design isclosely related to the precision and suitability of the models applied to circuits design. Thecharacteristic size becomes small, which makes the integration level and the processes complexitymuch higher, as well as the requirement for device model accuracy and model suitability. Then,devices modeling should guarantee to the accuracy of circuits simulation and the applicability ofadvanced technology.This paper mainly focused on RF CMOS devices in analog/radio frequency based on theprocess of IBM 90nm. The optimization of device performance is demonstrated through theanalysis of the structure of device layout, and then a new generation of CMOS industry-standardPSP model is applied to model the devices. From the device physical layout point, the RF devicemode with the clear physical meanings has been built.The paper first reviews the developments of MOSFET model, especially the developments ofPSP module, and then expatiates on the demands of RF CMOS device modeling and the purposeand significance of this topic to carry out, followed by the analysis of physical effects applied in thedeep submicron MOSFET device model and the introduction of a variety of higher-order effects.Then, the layout placement and routing for the impact on device performance are analyzed. On thebasis of the previous theoretical analysis, the devices are modeled based on PSP model. Themodeling process and results are given. The parasitic topology network of RF CMOS devices isdone by quantitative analysis, including parasitic resistance, parasitic capacitance and substratenetwork, and the sub-circuit network suited this work is given. This paper proposes the RF CMOSmodeling programs, and completes the RF CMOS devices modeling based on the parasitic topology network of RF CMOS devices. After the completion of the RF modeling, the comparison of themeasured values and simulation is given. Within the entire operating voltage range, the simulatedresults by the model are able to fit the measured S-parameters values well in the 100 MHz to 49.9GHz frequency range.At the end of this article, another device modeling method based on small signal equivalentcircuits analysis is proposed, so as to examine its high-frequency characteristics of RF MOSFEToptimized layout devices. The device structure is optimized by breaking the restriction of RFcharacteristics and the analysis of high frequency quality factor. Therefore, the forward-lookingoptimization of RF CMOS structure is provided.