Research Of LDPC Codes And Implementations Of FPGA Hardware Platform

LDPC codes are one class of linear block codes whose performance is close to Shannon limit.Because of their simple construction, lower decoding complexity and error floor, LDPC codes arewidely used in the field of telecommunication, and the research on them is a hot issue of channelencoding now.The methods of heoretical analysis, computer simulation and hardware platformimplementation are used to research in depth on encoding and decoding principle of LDPC codes,constructions of check matrices and develop of PCM/FM re-entry telemetry transceiver. The majorwork done is as follows:Firstly, a modified construction method of LDPC codes based on polynomial of cycles of PEG(Progressive-Edge-Growth) is proposed according to reaction on the performance of LDPC codesby polynomial of cycles based on PEG and connectivity of cycles. It can reduce the number of theshortest cycles, increase average local girth and improve connectivity of cycles while deleting shortcycles by considering girth of check matrix, number of the shortest cycles and ACE, so that it canimprove performance of decoding. At the same time, the method is also used to constructQC-LDPC codes. Simulation results show that the performance of this code is better thanunstructured Mackay code and it is easier for implementation on hardware.Secondly, a method for constructing QC-LDPC codes is proposed according to reaction on theperformance of LDPC codes based on Latin squares. It can eliminate short cycles and also improvethe shortcomings of original algorithm that the bit rate is not flexible when constructing codes byusing property of Steiner triple systems and Latin squares. Simulation results show that theproposed method is superior to short code PEG algorithm when constructing short codes; in theconstruction of long codes, it also have similar performance with PEG, and has an advantage ofeasier hardware implementation because of QC-LDPC codes.Thirdly, according to real-time and efficient demand of telemetry system for encryptionalgorithm, an encryption technical proposal based on key backward synchronization is designed toimprove the safety of telemetry data, to prevent third party from intercepting or using this information. The program uses the model of clock-controlled keystream generator, one timepadding encryption.Finally, an implementation of PCM/FM reentry telemetry system hardware platform isproposed according to the characteristics of reentry telemetry channel and after researching thedevelop status of hardware transceiver of reentry telemetry system. The implementation uses FPGA,including the modules of encryption, decryption, channel encoding, decoding, filter, FM modulationand demodulation. Detailed FPGA implementations of re-entry telemetry transmitter are given inthis paper, and the feasibility of encryption technical proposal is tested in the system.