The Study Of Correct Codes Based On FPGA

How to design the correct codes with high efficiency , good anti-interference and easy implementation equipment is the task of correct codes theory. The liner block correct codes are the most important block correct codes, so they are discussed in the thesis. Cyclical codes and LDPC codes both belong to the liner block correct codes.Firstly, using VHDL as the inputted language, this thesis gives the implementation of the coder, decoder of a cyclical code and a m_sequence generator based on VHDL. The simulation and analyses of the performance are given too. Secondly, the decoding algorithm and implementation scheme of LDPC codes are studied. With regard to the characteristic of LDPC codes, the thesis proposes a method to design the decoder using FPGA programming in C language. The programming model of LDPC decoder in C and Impulse C are designed. Finally, the decoder is implemented on hybrid FPGA/joint processor, and the excellent performance of LDPC codes is proved. A new idea is provided for soft engineers to develop embedded systems based on FPGA.