Research And Design Of Ultra Low Power CMOS Voltage Reference

With the rapid development of technology,various portable electronic devices have emerged in recent years.However,miniaturized and portable electronic devices have also brought some problems,and the battery life of the device has become a bottleneck restricting the application of electronic devices.How to reduce the power consumption of devices has become an important trend in the design and development of integrated circuits.It is an important and difficult point to reduce the power consumption of each circuit module in circuit design.The voltage reference source is an important module that is indispensable for electronic devices such as LDOs and ADCs.Stable output of a certain reference voltage can provide more stable performance for the latter circuit.The lowpower voltage reference can reduce the overall circuit system power consumption.Based on the theoretical characteristics of MOS devices,a sub-threshold property of MOSFET is used to study and design a nano-watt low-power full MOS voltage reference.In the design process,the following parts are improved and innovated: the whole circuit adopts NMOSFET and PMOSFET to realize the function,and does not use resistors,capacitors and inductors.In the design of the bias current generating circuit,the gate voltage control circuit is introduced to make the MOSFET work deep.The linear region replaces the traditional diffusion resistor structure,so that the bias current is in the nanoampere level,which significantly controls the power consumption of the overall circuit at the nanowatt level;improves the structure of the startup circuit,and introduces the front end stability in the design of the startup circuit.The voltage regulator preprocessing module greatly improves the power supply rejection ratio of the circuit at low frequencies,so that it can work normally under wide voltage,and the output reference voltage is almost unaffected;in the PTAT voltage compensation circuit,the differentiallike first-order multiple is adopted.The step compensation structure improves the threshold voltage of the MOS transistor due to the shimming effect accumulated in the conventional self-biased cascode structure due to the series connection.In order to verify the circuit design,this paper based on the 0.18?m CMOS process,pre-simulation of the designed circuit schematic on the Cadence software,using Virtuoso to design and draw the layout of the designed circuit diagram,passed the DRC and LVS test,and extracted The parasitic parameters are verified by simulation,and the design process from front to back is completed.The results of the pre-simulation and imitation are as follows: The voltage reference can work normally in the environment of-20?-80?,and the temperature coefficient is 41.55ppm/?.At 27?,the reference voltage of 525 mV can be stably output in the range of 1V-3.6V,the low-frequency power supply rejection ratio is less than-63 dB,the linear adjustment rate is only 0.011%,and the quiescent current of the whole circuit is about 57.5nA.The circuit consumes less than 70 nW and the total chip area is only 0.046 square millimeters.Compared with the published literature in recent years,some parameters of the nano-watt level low-power full MOS voltage reference source designed in this paper have certain advantages.