| In this work, the techniques of supply voltage reduction and threshold voltage adjustment are investigated as applied to CMOS adders. Multiple topologies of adder are compared as supply voltage is reduced to determine the optimal adder. SPICE simulations were performed on 32-bit adders implemented in 45nm High-K metal gate technology. There was no EDP benefit to reducing supply voltage below 0.4V. Threshold voltage adjustment is also investigated. An adder sized for minimal energy is operated at 10Mhz and 1 Mhz in 130nm, 45nm and 32nm technology. The older technology provides less leakage at lower threshold voltages, but increasing the threshold voltage and using a newer technology leads to an order of magnitude reduction in energy. Finally, supply voltage and threshold voltage are swept simultaneously. When threshold voltage is reduced to increase speed, supply voltages lower than 0.4V provide EDP reduction. |
